1. Field of the Invention
The invention relates in general to electronic circuits, and in particular, to electronic circuits of phase locked loops (PLL), and 3-stage frequency dividers.
2. Description of the Related Art
As device size scales down, CMOS devices are achieving higher operating speeds. The low power consumption and high circuit integration of miniaturized devices, along with the improvement of broadband techniques, make CMOS technology attractive in realizing ultra-fast phase locked loop (PLL) circuits.
FIG. 1 is a block diagram of a conventional PLL, comprising phase-frequency detector 10, charge pump circuit 12, voltage controlled oscillator (VCO) 14, and divider 16. Phase-frequency detector 10 is coupled to charge pump circuit 12, voltage controlled oscillator (VCO) 14, and divider 16, and back to phase-frequency detector 10 in a loop.
Phase-frequency detector 10 compares reference signal CKin with a feedback signal to determine a phase and frequency error therebetween to charge or discharge charge pump circuit 12. The accumulated charges in charge pump circuit 12 produce a control voltage to VCO 14 to generate clock signal CKout. Divider 16 receives clock signal CKout to perform a frequency division thereon to generate the feedback signal to phase-frequency detector 10 for phase and frequency error detection.
A number of considerations are taken into account for a PLL system, for example, parasitic capacitance in the PLL circuit may cause frequency shift of signals in the VCO or frequency divider to prevent the PLL from locking. Spurs in the reference signal also present an issue for conventional charge pump PLLs, where pulse-width comparison is performed in the phase detector, leading to interference problems to adjacent transmission channels. The reference clock feedthrough for conventional charge pump PLLs has always been an issue, wherein attempts have been made to minimize the reference spurs by: a charge transfer technique to spread out the momentary signal surge over a period; an analog phase detector using current-mode logic to reduce swing; a compensated charge-pump design to balance the device mismatch; and a distributed phase detector to avoid abrupt changes on the control voltage. However, none of the approaches eliminates pulse generation, so the control line ripple is never entirely removed.
Thus, a need exists for phase locked loop, voltage controlled oscillators (VCO), and phase-frequency detectors (PFD) to provide a high-speed and low-noise clock signal.